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16nm Zynq SoC mixes Cortex-A53, FPGA, Cortex-R5

Feb 27, 2015 — by Eric Brown — 4,770 views

Xilinx unveiled a 16nm “UltraScale+” version of its ARM/FPGA hybrid “Zynq” SoC with four Cortex-A53s cores, a faster FPGA, a GPU, and two Cortex-R5 MCUs.

The Linux-ready, Zynq UltraScale+ MPSoC is part of a major “UltraScale+” overhaul of Xilinx’s Kintex and Virtex FPGA product line, featuring a cutting edge, TSMC 16nm 3D FinFet process. This is much same process that will be used with the new ARM Cortex-A72 processors. Like the all-FPGA UltraScale+ FPGAs, the Zynq UltraScale+ MPSoC (Multi-Processing System on Chip) also features new memory block and interconnect technology, among other features. All the UltraScale+ processors, including the Zynq, will begin sampling by year’s end, with volume production in 2016.

Zynq UltraScale+ MPSoC architecture
(click image to enlarge)

The UltraScale+ 16nm FinFet process uses 3D packaging technology in addition to 3D FinFet transistors. This “3D-on-3D” technology enables two to five times greater system-level performance/watt than with previous Zynq, Kintex, and Virtex processors, claims Xilinx.

The process appears to be competitive with rival Altera’s Stratix 10 SX, system-on-chip, which uses Intel’s 14nm 3D Tri-Gate process. Like the new Zynq, the Stratix 10 SX combines a quad-core 64-bit ARM Cortex-A53 subsystem with floating-point DSP blocks and gigahertz-speed FPGA fabric.

Simplified Zynq UltraScale+ block diagram
(click image to enlarge)

According to EEJournal, the new Zynq is the most improved of the next-gen UltraScale+ processors. In part this is because the latest Kintex and Virtex have already moved to 20nm UltraScale designs, whereas the original Zynq-7000 was still at 28nm, but it also adds an unprecedented level of heterogenous processing on a single die.

The Zynq-7000 was similarly ground breaking. The SoC broke the common rules of system-on-chip design by integrating a pair of Linux-driven Cortex-A9 cores with an FPGA subsystem on a single die, linked by a high-speed AXI4 interconnect. This design, which preceded Altera’s similarly Cortex-A9/FPGA Cyclone V SoC, helped open up complex, but powerful FPGA fabric to Linux developers.

Major Zynq UltraScale+ components
(click image to enlarge)

Now, Xilinx has replaced the two Cortex-A9 cores with four, faster Cortex-A53 cores. As before, you’ll be able to choose from a range of models with varying levels of FPGA, but in this case, the higher levels are twice as powerful as before, with 914K logic cells, compared to 444K found in later high end Zynq models.

Perhaps the biggest enhancement is the addition of a pair of Cortex-R5 microcontroller units (MCUs) for improved real-time processing. The cores feature a vector FPU and a memory protection unit, as well as 128KB TCM with ECC cache, and 32KB each of I- and D-cache.

Freescale has used a similar hybrid strategy with its lower end, Cortex-A5/Cortex-M4 Vybrid-F SoC, and recently announced i.MX6 SoloX, which combines a Cortex-A9 and Cortex-M4 MCU. But whereas the SoloX Cortex-M4 can only be plumbed with Freescale’s MQX RTOS, it appears that a single PetaLinux SDK is designed to control the Cortex-M4, as well as the Cortex-A53 and FPGA, and other chips.

In addition to these three subsystems, the Zynq adds a Mali-400MP GPU, plus an an optional H.265/264 video codec and a DSP optimized for waveform and package processing. Also included is an analog MUX, power management chip, and a security and safety unit. All the cores are coordinated with “heterogeneous multi-processing” features, as well as a new SmartConnect.

Full Zynq UltraScale+ block diagram
(click image to enlarge)

The SmartConnect technology, which is also used in the UltraScale+ Kintex and Virtex designs, enables the optimization of each interconnect between processing blocks rather than simply applying a universal interconnect throughout the SoC. Another key UltraScale+ feature is “UltraRAM,” a new type of memory block that offers more on-chip capacity with faster performance and reduced latency.

Major features of the Zynq UltraScale+ MPSoC and other UltraScale+ processors include:

  • 16nm 3D FinFet process and other enhancements for 2-5x greater system-level performance/watt compared to over 28nm Xilinx devices
  • UltraRAM for massive on-chip memory and SRAM device integration
  • SmartConnect IP interconnect optimization technology for an additional 20-30 percent advantage in performance/watt
  • High-speed memory cascading to remove bottlenecks in DSP and packet processing
  • Enhanced DSP slices incorporating 27×18-bit multipliers and dual adders, enabling a massive jump in fixed- and IEEE Std 754 floating-point arithmetic performance and efficiency
  • Step-function increase in 3D IC inter-die bandwidth for virtual monolithic design
  • Massive I/O bandwidth and dramatic latency reduction through multiple integrated ASIC-class blocks for 100G Ethernet with RS-FEC, 150G Interlaken, and PCIe Gen4
  • Static- and dynamic-power gating across a wide range of functional elements, “yielding significant power savings”
  • Next-generation security with advanced approaches to AES bitstream decryption and authentication, key-obfuscation, and secure device programming
  • DDR4 support of up to 2,666Mbps for massive memory interface bandwidth
  • MPSoC technology (Zynq only) combining soft and hard engines for real time control, graphics and video processing, waveform and packet processing, and multi-level security, safety and reliability, and more

The Zynq UltraScale+ will be available in a Smarter Control & Vision family, as well as a higher end Smarter Network family, each with a variety of models. The network version, which lacks the optional video codec, primarily differs in its greater FPGA features, which extend up to 1,095K effective LEs, 920K logic cells, and 3,528 DSP slices, and higher speed serial transceivers.

Both Zynq families feature DDR4 support, as well as peripherals support including USB 3.0, SATA 3.0, DisplayPort, quad tri-mode gigabit Ethernet, and four PCIe Gen 2 interfaces. Their FPGA systems additionally offer eight PCIe Gen 4 lanes and 16 Gen 3 lanes. There’s also a variety of general I/O support, including USB 2.0, SDIO, UART, CAN, I2C, SPI, and GPIO.

The new Zynq SoCs are supported with the Xilinx PetaLinux distribution, SDK, and board support package Also available is the Vivado Design Suite, as well as support for C++, SystemC, OpenCL, OpenCV, MATLAB, and LabView, says Xilinx.

Further information

Early access to the UltraScale+ processors starts in the second quarter, with samples coming later this year, and volume production due in 2016. More information may be found at the Zynq UltraScale+ product page.

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0 responses to “16nm Zynq SoC mixes Cortex-A53, FPGA, Cortex-R5”

  1. Steve VanderLeest says:

    Xilinx selected DornerWorks to provide the Xen hypervisor support for this new chip. The expected use-case is to have TrustZone manage the two processors, putting a simple, secure or real-time OS on the RPU and putting a more general-purpose hypervisor (like Xen) on the APU.

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