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First Linux-ready 32-bit Warrior core among new MIPS chips

Nov 10, 2015 — by Eric Brown — 1,298 views

Imagination has launched the fastest 64-bit MIPS Warrior core yet with its P6600, as well as the M6250, the first 32-bit Warrior-M CPU that runs Linux.

Imagination Technologies announced the availability of three new processor IP designs based on its latest MIPS Release 6 architecture. Leading the way is the Warrior-P class P6600 — its fastest Warrior yet. There are also two low-end Warrior-M chip designs: an M6200 for RTOSes, and an M6250 that stands out as the first Warrior-M processor to run Linux.

The high-end P6600 follows up on the MIPS Series5 Warrior-P5600 processor unveiled in Oct. 2013, following the original announcement of the Warrior family in June of that year. While the P5600 is 32-bit, the new P6600 is 64-bit, and the most powerful Warrior processor to date, with up to 2GHz performance in up to hexacore designs. A Warrior I6400 design that arrived in Sept. 2014 is 64-bit, but from the second-ranked Warrior-I family.

Warrior P6600 block diagram
(click image to enlarge)

The Warrior P6600 is aimed at higher-end mobile, home entertainment, networking, and automotive applications. Although Imagination makes no reference to OS support here, the earlier Warrior-P and Warrior-I processors supported Linux and Android.

Imagination’s two 32-bit Warrior-M class processors target low-power embedded IoT and consumer electronics applications. Like the earlier, wearables-focused Warrior M51xx, the new M6200 is designed for 32-bit microcontrollers running real-time operating systems (RTOSes), but supports more sophisticated embedded applications. The M6250, meanwhile, is specifically called out as a more advanced 32-bit design for Linux and other advanced OSes (see farther below).

All three chips run on a new MIPS Release 6 architecture, which for the first time provides full compatibility between MIPS64 and MIPS32 ISAs. The updated architecture is also said to increase peak performance while reducing footprint and power consumption.

MIPS Release 6 is based on the same fixed-length, regularly encoded instruction set, and same load/store data model, as earlier MIPS processors. The updated architecture supports optimized execution of high-level programming languages, with arithmetic and logic operations that use a three-operand format, allowing compilers to optimize complex expressions formulation, says Imagination. The architecture provides 32 general-purpose registers to enable compilers to further optimize code generation by keeping frequently accessed data in registers, says the company.

Warrior P6600

The 64-bit P6600 is based on the 32-bit P5600 design, and is said to be a “straightforward upgrade.” Like the 64-bit I6400, the processor is available in configurations ranging from single to hexacore clusters, with clock rates of between 1GHz and 2GHz per core.

Total CoreMark benchmarks achieve a score of >7500 per core and Total DMIPS benchmarks achieve >5250 per core, claims Imagination. Each core cluster implements per-CPU dynamic control of voltage and/or frequency, thereby further increasing performance and power management, says the company.

Warrior P6600 in a basic hexacore SoC design
(click image to enlarge)

The P6600 combines a deep 16-stage pipeline with multi-issue, Out-of-Order (OoO) execution optimized for “today’s complex software workloads,” says Imagination. The design is also touted for its “best-in-class” branch prediction, including a fully associative Level 1 BTB (branch target buffer) and an improved Level 2 cache sub-system, as well as an improved load/store instruction bonding mechanism. There’s also a “super-fast,” 128-bit SIMD engine for accelerating multimedia processing tasks such as VP9 encoding with efficient parallel processing of vector operations.

Like the P5600, the P6600 supports Imagination’s OmniShield secure virtualization platform, which was announced last May. The P6600 can tap OmniShield to coordinate up to 15 guest OSes running simultaneously in fully isolated and trusted environments, says Imagination.

Warrior M6250 and M6200

While the Linux-oriented M6250 and RTOS-focused M6200 are Warrior chips, they borrow from Imagination’s lower-end MicroAptiv processor family. Some MicroApriv models can run Linux in a limited way, but MicroAptiv is principally designed for microcontrollers running RTOSes. A version of MicroAptiv was spun off earlier this year as an open source MIPSfpga processor design for academic researchers.

Block diagrams for the Linux-ready M6250 (left) and the RTOS-destined M6200
(click images to enlarge)

The M6250 is based on the MicroAptiv UC (MPU) design while the M6200 is based on the MicroAptiv UP (MPU). Both designs, which operate at up to 750MHz on their single cores, can run at upt to 30 percent higher frequencies than their corresponding MicroAptivs, claims Imagination.

With core areas of only 0.23mm (M6250) and 0.19mm (M6200) squared, and core power (µW/MHz) ratings of 62 and 60, respectively, the processors are said to be ideal for low-power, small-footprint devices. Applications are said to include wireless or wired modems, GPU supervisors, flash and SSD controllers, industrial and motor control, and advanced audio.

Features shared by both new Warrior-M chips include:

  • 6-stage pipeline designs with MIP32 Release 6
  • Support for MicroMIPS32 ISA, a set of optimized 16-bit and 32-bit instructions for significant reductions in code size with a performance equivalent to MIPS32
  • Tightly coupled memory (TCM) for high-performance applications
  • Interrupt controller supporting up to 256 interrupts
  • Support for MIPS DSP Module Revision 3 as a configurable option, providing a higher level of DSP-like processing and SIMD support.
  • ECC and parity protection on instruction and data memories as a configurable option for increased reliability
  • New AMBA APB interface enabling JTAG, multicore, and mixed-core debugging

While the MCU-focused M6200 includes an SRAM controller and 64-bit instruction and data SRAM interfaces, the M6250 provides additional features, most notably including a Linux-friendly Memory Management Unit (MMU). The M6250 also provides a memory controller that supports instruction/data L1 cache and optional, tightly coupled ScratchPad RAMs (SPRAMs), says Imagination.

The M6250 is further equipped with a high-speed 64-bit AXI3 bus interface, as well as data and instruction cache controllers. There’s also support for eXtended Memory Addressing (XPA) to 40-bit physical address space for up to 1TB of system memory.

It will be interesting to see if Imagination Technologies releases a community-backed development board such as the Creator C120 based on the M6250. The new chip would be slower, but also more power efficient than the C120’s dual-core, 1.2GHz Ingenic JZ4780 SoC, which uses an older MIPS32 IP version released prior to Warrior.

Further information

The Warrior M6200, M6250 and P6600 designs are available now for licensing. More information may be found on the Imagination Technologies product pages for the M6200 and M6250, as well as the P6600.

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