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First SoCs based on open source RISC-V run Linux

Jul 11, 2016 — by Eric Brown — 1,966 views

SiFive unveiled the first embedded SoCs based on the open source RISC-V platform: A Linux-ready octa-core Freedom U500 and a FreeRTOS-based Freedom E300.

A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform. At the RISC-V 4thWorkshop at MIT this week, SiFive announced two embedded SoC families. The Freedom Unleashed family debuts with a 28nm fabricated, Freedom U500 SoC with up to eight 1.6GHz cores that runs Linux, aimed at machine learning, storage, and networking applications. The MCU-like Freedom Everywhere family for Internet of Things starts with a 180nm Freedom E300 model that runs FreeRTOS.

Like RISC-V, both designs are fully open source, but the company also plans to sell finished SoCs with the help of fabrication partner TSMC. The platform will “reverse the industry’s prohibitively rising licensing, design and implementation costs,” says SiFive.

The San Francisco based company has released full specs for the designs, which appear to be sampling. It’s unclear when volume production is planned, but developers can now run “full FPGA models” of either SoC on a Microsemi SF2+ development board built around Microsemi’s Cortex-M3-based SmartFusion2 SoC FPGA. The U500 is further supported with FPGA development boards from Xilinx and Digilent (see farther below).

Microsemi SmartFusion2 SoC FPGA block diagram
(click image to enlarge)

The 64-bit RISC-V architecture was unveiled at the University of California several years ago, and has been further developed since then. RISC-V is pitched as an alternative to proprietary architectures like Intel x86, ARM, PowerPC, and MIPS.

SiFive is one of several companies working on a RISC-V SoC. Two years ago a University of Cambridge spinoff called lowRISC announced plans to develop a Linux-based SoC and development board based on the RISC-V ISA. The lowRISC website now says it will “tape out our first volume chip this year.”

Other RISC-V Platinum members include SiFive along with a wide range of startups and tech heavyweights. These include, but are not limited to, Draper, Google, Hewlett Packard Enterprise, IBM, Microsemi, Oracle, Microsoft, Nvidia, and Qualcomm. Gold members include AMD, Espressif, Intrinsix, among others, and Silver members include ETH Zurich, Gray Research, Lattice, MIT CSAIL, and many others, including lowRISC.

According to Forbes, SiFive was founded by RISC-V inventors including Yunsup Lee, Andrew Waterman, and Krste Asanovic, and has been funded by Sutter Hill Ventures. In 2014, Asanovic and fellow UC Berkeley professor David Patterson, who originally coined the term RISC (Reduced Instruction Set Computer), posted a white paper on RISC-V.

The white paper argued that a fully open ISA like RISC-V would encourage more free-market competition and innovation, faster time to market via open source methodology, and more affordable processors. RISC-V builds upon two earlier open source RISC ISAs — SPARC and OpenRISC — and seems to have largely eclipsed both efforts.

Aside from being open source, one of the main benefits of RISC-V is that it is fully modern, purpose built, and unburdened with legacy code. “We had the luxury of starting in 2010,” SiFive CTO Yunsup Lee told Forbes. “RISC-V is clean and modern and very simple to implement.”

RISC-V ISA reference card (parts 1 and 2)
(click images to enjoy)

RISC-V was originally designed as a Linux-focused Cortex-A5 competitor for IoT. Judging from SiFive’s designs, however, the spectrum has grown much broader than that, ranging from the high-end embedded Linux Freedom U500 to the MCU-like, IoT-oriented Freedom E300.

The breadth and open source foundation of the platform provide plenty of benefits, but could also undermine the platform due to fragmentation and incomplete compatibility, notes Charlie Demerjian in SemiAccurate. SiFive’s answer to this, he wrote, is that SoC vendors tapping the designs are fully aware of this danger and will self-police accordingly to limit fragmentation.

Freedom U500

The Freedom U500 can integrate up to eight 64-bit, cache coherent “U5 Coreplex” RISC-V cores clockable today to 1.6GHz, and perhaps higher in the future. The U5 Coreplex supports the RV64GC RISC-V variant

Block diagrams: U5 Coreplex (left) and Freedom U500 SoC
(click images to enlarge)

Each U5 core has a single-issue, in-order 64-bit execution pipeline, with a peak sustained execution rate of one instruction per clock cycle. The cores include a dynamic branch prediction scheme, including BTBs, BHTs, and return-address stacks, says SiFive. The design includes private L1 caches and a shared L2 cache in various configurations.

The Freedom U500 can accept a variety of custom accelerators, and is available with an optional “RV64IMACN” monitor core for secure boot. The SoCs can support up to four 72-bit DDR3/4 DRAM channels, with full ECC support, providing up to 68GB/s of memory bandwidth.

The U500 supports high-speed interfaces including Gigabit Ethernet, Dual Mode PCIe Gen 3.0 expansion, and USB 3.0, including OTG. These interfaces can master directly into the cache-coherent memory system, and can optionally allocate data directly into L2 cache, says SiFive.

Peripheral support includes counter/timers, watchdogs, PWM, GPIO, UART, I2C, SPI, ADC, DAC, and SD/eMMC flash. In addition, third-party peripheral IP can be attached via industry-standard SoC buses or TileLink, says SiFive. The design includes a configurable, platform-level interrupt controller, as well as power management with Always-On Block (AON) for low-power sleep mode.

The Freedom U500 supplies platform-level debug features, including hardware breakpoints, watchpoints, and single-step execution accessed via JTAG, complete with open-source debug tools. The open source RISC-V software development toolchain is available via a Linux BSP with device drivers, C and C++ compilers, standard libraries, assemblers, and linkers.

Developers can customize the SoC design themselves or hire SiFive to do it. Customizations include custom instruction-set extensions, coprocessors, accelerators, I/O, and AONs. SiFive also provides a variety of development boards for the U500 (see farther below).

Freedom E300

The Freedom E300 is built around a 180nm, microcontroller-like “E3 Coreplex” core. The E3 Coreplex supports RISC-V ISA variants include RV32E (16 user registers) and RV32I (32 user registers). The core has a single-issue in-order 32-bit execution pipeline, with a peak sustained execution rate of one instruction per clock cycle. It can optionally implement prefetch buffers, as well as an instruction cache to accelerate instruction fetch. Several static and dynamic branch prediction schemes are also available.

Block diagrams: E3 Coreplex and Freedom E300 SoC
(click images to enlarge)

The E3 Coreplex can be extended with new custom instructions that operate on the existing user registers, or with custom coprocessors, says SiFive. Custom accelerators can directly access on-chip memories and peripheral devices, and can generate and receive interrupts from the platform-level interrupt control.

The E300 SoC’s memory system supports ROM, OTP, eFlashy, NVM/EEPROM, and SRAM. Peripheral support includes counter/timers, watchdogs, PWM, GPIO, UART, I2C, SPI, ADC, DAC, SD/eMMC, and USB 1.1/2.0 OTG. A central, autonomous DMA engine is available for reducing processor overhead during I/O transfers.

Other features include a configurable platform-level interrupt controller, power management with AON, and various debug facilities including JTAG. The open source FreeRTOS-based toolchain includes much the same capabilities as those provided by the U500.

Development Boards

The SiFive announcement notes only the availability of a development platform based on Microsemi’s SmartFusion 2 SoC FPGA. However, the SiFive website lists SmartFusion 2 based boards only for the Freedom E300, while the U500 is supported by FPGA-based boards from Xilinx and Digilent.

Freedom E300 dev boards: Arrow’s SF2+ (left) and EmCraft’s M2S060
(click images to enlarge)

For the Freedom E300 the main platform is Arrow’s $125 SF2+ Development Kit. Listed as an option is EmCraft’s $165 SOM-M2S060-FG484I. Both boards are built around Microsemi’s SmartFusion 2 SoC.

Freedom U500 dev boards: Xilinx Virtex-7 VC707 (left) and Digilent’s Arty Board Artix-7
(click images to enlarge)

The Freedom U500 is available either with a $3,495 Xilinx Virtex-7 VC707 FPGA Dev Kit or a $99 Digilent Arty Board Artix-7 FPGA Development Board. The latter, which is focused more on application development than hardware design, lacks the VC707’s support for “high speed serial interfaces or high speed prototyping,” says SiFive. The Xilinx VC707 is available with optional PCIe FMC modules and switches.

Further information

Full documentation and sign-up for development boards are now available for the Freedom U500 (Linux) and Freedom E300 (FreeRTOS) RISC-V SoCs. More information may be found on the SiFive developers site.

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2 responses to “First SoCs based on open source RISC-V run Linux”

  1. David says:

    Great news!

  2. guest says:

    Yes, great news so far. But what is really needed to take this off is a net-/notebook on Kickstarter (I want a net-/notebook, not a Raspberry Pi type thing, as one would need to add a keyboard, display, …, although that would be still better than nothing). Must not be 1080 IPS, 1388 or so TN panel would be enough too. 1080 IPS and all the extras could become an achievement in the Kickstarter process later.

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