All News | Boards | Chips | Devices | Software | Archive | About | Contact | Subscribe
Please whitelist in your ad blocker. Without ads from our sponsors, we cannot continue publishing this site. Thanks :-)

Linux-optimized IP core promises 4200 DMIPS

Oct 20, 2014 — by Eric Brown — 1,518 views

Synopsis announced an “HS38” version of its Linux-focused DesignWare ARC core IP with a new ARCv2 ISA and support for 2.2GHz, 4200 DMIPS speeds at 28nm.

Synopsis acquired its Linux-optimized line of DesignWare ARC 32-bit RISC/DSP cores when it bought semiconductor IP vendor Virage Logic back in 2010 shortly after Virage acquired ARC International. Since then Synopsis has released several DesignWare ARC HS processor designs, most recently with the HS36.

The HS38 steps up to an ARCv2 instruction-set architecture (ISA), which is said to lower power consumption, reduce silicon footprint, and improve performance. Optimized for embedded Linux, the HS38 consumes less than 90 milliwatts of power, and occupies only 0.21 mm2 of silicon area, according to Synopsis.

The HS38 provides 4200 DMIPS performance when clocked to 2.2GHz using a 28nm fabrication process, claims the company. This 1.93 DMIPS/MHz performance ratio is said to be to be twice that of the ARC 770D cores that preceded the HS line.

DesignWare ARC HS38 block diagram
(click image to enlarge)

The HS38 is ideally suited for embedded control and signal processing tasks, says Synopsis. These are said to include devices such as home routers and gateways, data centers, digital TVs, networked appliances, and automotive infotainment,

The HS38 provides a “full-featured” memory management unit (MMU) supporting a 40-bit physical address space and page sizes up to 16MB. This enables direct access to 1TB of memory “with faster data access and higher system performance,” says the company.

The HS38 supports dual-and quad-core configurations, including support for SMP Linux, full L1 cache coherency, and up to 8MB of L2 cache. An optional floating-point unit (FPU) supports single- and double-precision arithmetic instructions. The “highly configurable” HS38 can be extended with user-defined hardware accelerators that are “tightly coupled” to the processor core, says Synopsis.

ARC HS features that are continued on the HS38 include support for close coupled memories and direct mapped peripherals “with single cycle access to all peripheral registers on an SoC,” says Synopsis. ARC Processor EXtension (APEX) technology is said to enable user-defined hardware to be added to the core through custom instructions or user-supplied RTL, accelerating application-specific code while reducing power. Other touted features include support for I/O coherency, as well as native ARM AMBA AXI and AHB standard interfaces that are configurable for 32- or 64-bit transactions

ARC development tools

Synopsys offers a MetaWare Development Toolkit for debugging and optimizing embedded software on ARC processors. The kit includes an optimized C/C++ compiler, a debugger, and a fast instruction set simulator (ISS) for pre-hardware software development.

An ARC HS Processor Family Virtualizer Development Kit (VDK) integrates a processor with common peripherals to use as a virtual prototype. Other tools include a “fully cycle-accurate” simulator for design optimization and verification.

The HS38 is supported with open source software including an optimized Linux kernel, the GNU Compiler Collection (GCC), the GNU Project Debugger (GDB), and associated GNU programming utilities (binutils). An ARC AXS103 Software Development Platform is available for software development on hardware. The AXS103 kit provides peripherals, drivers, pre-built Linux images, and application examples.

An ARC HS38 technology plug-in for Synopsys’ Lynx Design System, provides pre-tuned design flow scripts, constraints and tool settings for accelerating chip-level integration and “time to optimized results,” says Synopsis. Third party ARC tools are also said to support the HS38 design.

“We selected the ARC 770D for our NPS-400 network processor because of its unique combination of high performance and low power, along with its extensible instruction set,” stated Guy Koren, CTO at EZchip Technologies. “The new ARC HS38 provides an exciting upgrade path, delivering much higher performance with the same number of processors, and improved overall channel density. A critical component of the NPS-400 project was support for SMP Linux to ease our customers’ software programming. Our collaboration with Synopsys resulted in an optimized SMP Linux kernel, which will benefit ARC HS38 users as well.”

“The systems deployed in home routers, mobile internet and auto infotainment applications are becoming increasingly complex, demanding greater functionality and performance without increasing energy consumption,” stated Linley Gwennap, principal analyst of The Linley Group. “With its 40-bit physical address space, L1 cache coherency and L2 cache support, the ARC HS38 processor is uniquely positioned to address the needs of these rapidly evolving high-end embedded applications, now and in the future.”

Further information

The DesignWare ARC HS38 Processor, ARC HS Family VDK, and ARC AXS103 Software Development Platform will be generally available in December. The MetaWare Development Toolkit, Linux kernel, and GNU Toolchain are available now. More information may be found on the DesignWare ARC HS38 product page.

(advertise here)


0 responses to “Linux-optimized IP core promises 4200 DMIPS”

  1. Curt Wuollet says:

    It’s finally happened, the state of the art has advanced to the point where a product review appears as gibberish to an old ML and assembly programmer:^).

  2. Dev says:

    There are some marketing gimmics yes but what is so gibberish here ? Dhrystone ? Or coherency ?

Please comment here...