Imagination announced a 64-bit Warrior processor with a MIPS I6400 core that features hardware virtualization, multi-threading, and multi-clustering.
Imagination unveiled its I-Class Warrior processor featuring a new family of 64-bit MIPS I6400 cores, thereby filling in the high end of its Warrior family. The new I6400 cores are primarily designed for SoCs used in servers and networking gear, and much like earlier MIPS64 cores have been used in Linux-oriented system-on-chips like Cavium’s carrier-grade Octeon III or Broadcom’s XLR. However, for the first time, 64-bit MIPS cores are also being promoted as a mobile solution.
Warrior-I i6400 core block diagram
(click image to enlarge)
Imagination’s Warrior family of 32- and 64-bit processors was first introduced in June 2013. In October, the UK-based semiconductor IP designer followed up with the launch of the 32-bit MIPS Series5 Warrior-P processor, featuring new MIPS P5600 cores said to offer up to twice the performance of earlier 32-bit cores.
On the low end, Imagination earlier this year announced a Warrior-M design for Internet of Things and wearables, including Warrior M5100 and M5150 processors. These are claimed to be the world’s first MCU-class CPU IP cores with hardware virtualization. Warrior-M is supported by a new family of MIPS-based system-on-chips from Ineda Systems, called Dhanush Wearable Processing Units.
Inside the I6400
Key features of the Warrior-I family and I6400 cores include:
- Multi-threading — The I6400 core’s hardware multi-threading supports up to four hardware threads per core. It features simultaneous multi-threading (SMT) technology that enables execution of multiple instructions from multiple threads every clock cycle. Adding a second thread leads to performance increases of 40-50 percent, with less than a 10 percent cluster area increase, claims Imagination. Among other benefits, this is said to speed real-world applications such as browsers.
- Virtualization — Like other Warrior cores, the the I6400 integrates hardware virtualization technology, “enabling a unified security and virtualization strategy throughout the system and across the entire SoC,” said Imagination The I6400 supports up to 15 secure or non-secure guests.
- Security — For added security, the core supports multiple independent security contexts and multiple independent execution domains. The security technology enables secure content delivery, secure payments, and identity protection, says Imagination.
- Power management — New “PowerGearing” power management capabilities include the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster. At the same time, PowerGearing maintains coherency across CPUs so that sleeping cores “only need to wake when needed,” says the company.
- FPU — The I6400’s hardware Floating Point Unit (FPU) is said to support single and double precision capabilities, and offers improved control systems processing.
- 128-bit SIMD — New 128-bit SIMD (single instruction, multiple data) support is said to exploit the efficiencies of SIMD execution in data-parallel applications for greater performance and throughput. The SIMD technology supports high-level languages such as C or OpenCL, and can also leverage existing code. The SIMD supports 8-, 16-, 32-, and 64-bit architectures, as well as 32- and 64-bit floating point data types.
- Coherency Manager — SoC designers implementing the I6400 cores in multicore SoCs can draw upon a new MIPS Coherency Manager fabric based on a new multicore coherent interconnect architecture (see block diagram below). The Coherency Manager supports up to six cores per cluster, with multiple cores on a single cluster. Each core can have different synthesis targets and different clock frequencies and voltages. Other features include hardware pre-fetching, as well as wider buses and lower latencies compared to earlier MIPS64 processors.
- Multi-cluster coherency — The I6400 architecture is designed to support multi-cluster fabric configurations of up to 64 clusters. The cores can also operate in heterogeneous clusters in SoC implementations that integrate CPUs, GPUs and other processing elements.
MIPS I6400 Coherent Multicore System (i.e., a very basic multicore SoC design)
(click image to enlarge)
Prpl support and Android L
The I6400 is supported by Imagination’s “Prpl” open source ecosystem foundation for MIPS software development. Prpl founders include Broadcom, Cavium, Ikanos, Ineda Systems, Ingenic Semiconductor, Lantiq, PMC, and Qualcomm.
Development tools and software are already available or in development for the I6400 from Imagination and other partners, says the company. For example, Prpl has already released a version of the QEMU open source emulator that supports MIPS64 r6, available on Github.
Imagination notes that the forthcoming Android L release release, due this fall, includes support for 64-bit MIPS. In a blog post, Imagination technology marketing specialist Alexandru Voica stated, “MIPS I6400 includes state of the art technologies like SIMD and multi-threading that make a big difference for Linux-based operating systems (Android, Firefox OS, Tizen, etc.) and the most widely used applications in mobile such as web browsing and multimedia processing.”
“This is the MIPS Warrior core that many have been waiting for,” stated Tony King-Smith, EVP marketing, Imagination. “The I6400 is more efficient, flexible and scalable than the competition, and its feature set clearly lends itself to the needs of a wide range of next-generation applications including smartphones and tablets.”
General availability of the I6400 core is scheduled for December. Much more information may be found at the Imagination Technologies I6400 product page.