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Renesas goes 64-bit for latest automotive R-Car SoC

Dec 3, 2015 — by Eric Brown — 2,131 views

Renesas unveiled its latest R-Car H3 automotive SoC, with four Cortex-A57 and four Cortex-A53 cores, a PowerVR GX6650 GPU, and ISO 26262 safety compliance.

Renesas has announced initial samples of a third generation R-Car automotive system-on-chip. Like the R-Car H2 system announced in early 2013, the R-Car H3 is an octa-core chip using ARM Big.Little technology. The H3, however, is fabricated with a 16nm process, and moves from Cortex-A15 and -A7 cores to 64-bit Cortex-A57 and -A53 cores. The initial H3 model, which is scheduled for mass production in March 2018, targets both IVI and driving safety support systems.

R-Car H3 block diagram
(click image to enlarge)

The R-Car H3 can process large volumes of information from vehicle sensors accurately in real-time, enabling obstacle detection, driver status recognition, hazard prediction, and hazard avoidance applications, says Renesas. The SoC complies with the ISO 26262 (ASIL-B) safety standard, enabling “driving safety support systems,” a description that appears to overlap with the more commonly used term ADAS (advance driver assistance systems). The H3 can also boost IVI applications by supporting an expected increase in interactions with mobile devices and cloud services, says the company.

Like TI’s similarly Linux- and Android-ready Jacinto 6, the Renesas R-Car is one of the leading ARM-based automotive system-on-chips in the market. Renesas cites a Strategy Analytics report claiming that it was the 2014 leader in terms of revenue among in-vehicle infotainment (IVI) SoCs.

R-Car roadmap
(click image to enlarge)

The octa-core SoC delivers an aggregrate of 40,000 DMIPS performance, up from 25000 DMIPS on the H2, claims Renesas. The four Cortex-A57 cores share 48KB and 32KB L1 caches, as well as a 2MB L2 cache. The Cortex-A53 cores share two 32KB L1 caches and a 512KB L2.

The GPU advances from a PowerVR G6400 to a PowerVR GX6650, delivering three times the shader calculation performance, according to Renesas. Announced in January at CES, the 192-core PowerVR GX6650 is billed by Imagination Technologies as “the most powerful GPU IP core available today.”

PowerVR GX6650 block diagram
(click image to enlarge)

The GPU provides six Unified Shading Clusters (USCs), and can process 12 pixels per clock. It features PowerGearing G6XT power management, and a low-power, high-performance FP16 mode that can deliver up to twice the performance of FP32 within a constrained power budget, says Imagination. It does not appear that this model is any better documented than any other PowerVRs, although there was a hint earlier this year that Imagination may be moving in a more open direction.

The R-Car H3 moves from the Renesas IMP-X4 parallel programmable image processing core to an IMP-X5 chip that’s claimed to offer four times the image recognition performance. There’s also an audio DSP, as well as a a video codec engine claimed to offer twice the playback performance as the video coprocessor in the H2.

The third-gen R-Car is further equipped with a “dual lock-step” Cortex-R7 MCU, security and stream engines, plus a more robust boot protection process, says Renesas. The SoC provides four times the memory bandwidth of the H2, and is available with SiP modules that reduce PCB costs and complexities, says Renesas. These include CPU and LPDDR4-1600 RAM modules and serial flash modules for boot-up.

The SoC supports interfaces including 3-channel display output, 8-channel video input, and PHYs for a single USB 3.0 port and two USB 2.0 ports. Other supported I/O includes Ethernet, SD, SATA, multimedia card, MLB, MOST, CAN, PWM, I2C, SCIF, and more. A PCI Express 2.0 bus is available for connecting a WiFi/Bluetooth module, and a digital radio I/F interface supports other radios.

The H3 provides software scalability from the previous R-Car H2, M2, and E2 designs, says Renesas. Supported operating systems are said to include Linux, Android, QNX, Neutrino, Integrity, and “others.” An evaluation board will be available, although there appear to be no further details other than that it “Includes car information system-oriented peripheral circuits, providing users with an actual device verification environment; Can be used as a software development tool for application software, etc.” and “Allows easy implementation of custom user functions.”

“The R-Car H3 SoC has the all-round sensing, efficiency and safety characteristics that are essential in connected car technologies,” stated James McNiven, general manager, CPU group, ARM.

Further information

Samples of the R-Car H3 are available now. Mass production is scheduled to begin in March 2018, and is expected to reach a volume of 100,000 units per month in March 2019. More information may be found in the Renesas R-Car H3 announcement and product page.

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