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Xilinx adds dual core Cortex-A53/FPGA Zynq SoC model

Jun 15, 2016 — by Eric Brown — 1,019 views

Xilinx unveiled a dual-core “CG” version of its Cortex-A53/FPGA Zynq UltraScale+ MPSoC, and Mentor Graphics announced Android 5.1 and Linux support.

Back in Feb. 2015, Xilinx announced its next generation Zynq UltraScale+ MPSoC (multiprocessor system-on-chip) follow-on to its popular Zynq 7000 hybrid ARM/FPGA system-on-chips. The 16nm, quad-core Cortex-A53 SoC, which features a faster FPGA, a GPU, and two Cortex-R5 MCUs, has reached production, and now Xilinx has revealed a dual-core “CG” version of the SoC due to ship in the first half of 2017.

The CG SoC is aimed at industrial motor control, sensor fusion, and industrial IoT applications. By contrast, the flagship, quad-core EG model targets next-generation wired and 5G wireless infrastructure, cloud computing, and aerospace and defense applications. In addition to the CG announcement, Mentor Graphics announced Android 5.1 and Mentor Embedded Linux support for the entire UltraScale+ MPSoC family (see farther below).

Zynq UltraScale+ MPSoC CG block diagram
(click image to enlarge)

Xilinx is rumored to have recently received a $15 billion acquisition offer, with earlier rumors pointing to Qualcomm as the potential suitor. Last year, Intel acquired rival Altera, which has its own quad-core, 64-bit Cortex-A53 Stratix 10 SX SoC. Like the Zynq UltraScale+ MPSoC, the Stratix 10 SX combine Cortex-A53 cores with FPGA fabric. The dueling SoC families also similarly feature state-of-the-art fabrication processes, with the Stratix 10 using Intel’s 14nm 3D Tri-Gate process and Xilinx tapping a TSMC 16nm 3D FinFet process for the UltraScale+ MPSoC, including the new CG.

The Zynq UltraScale+ MPSoC CG version joins the flagship, quad-core EG model, and similarly offers a new SmartConnect interconnect technology that is claimed to provide a 20-30 percent advantage in performance/watt. SmartConnect enables the optimization of each interconnect between processing blocks rather than simply applying a universal interconnect throughout the SoC. Another key UltraScale+ feature is “UltraRAM,” a new type of memory block that offers more on-chip capacity with faster performance and reduced latency.

Like the EG, the CG similarly offers dual-core Cortex-R5 microcontrollers with vector FPUs and memory protection units. The CG’s dual Cortex-A53 cores are clocked to 1.3GHz rather than 1.5GHz on the EG, and its MCUs are clocked to 533MHz instead of 600MHz.

The six CG sub-models have FPGAs starting at 103K system logic cells, which is slightly more than the 85K cells offered on the first-gen, dual Cortex-A9 Zynq-7020, and ranging all the way up to 600K. In other measures of FPGA performance, CLB flip-flops range from 94 to 548, and CLB LUTs go from 47 to 274. By contrast, the EG ranges from 103K to 1,143K logic cells, 94 to 1,045 flip-flops, and 47 to 523 LUTs.

The new CG lacks the EG’s ARM Mali-400 MP2 GPU, as well as its super high-speed connectivity. For example, it’s limited to Gigabit Ethernet, while the EG adds options such as 100Gbps Ethernet and 150Gbps Interlaken links.

Block diagrams for the EG (left) and EV models
(click images to enlarge)

Since the original announcement, Xilinx has added a EV model that is much like the EG, including the four 1.5GHz Cortex-A53 cores, 600MHz Cortex-R5 MCUs, and Mali-400 MP2 GPU. The EV adds a H.265/H.264 video codec that supports simultaneous encode and decode up to 4Kx2K @ 60fps.

The EV shares the connectivity limits of the new CG, and its FPGA range falls in between the CG and EG at a tighter mid-range of 192K to 504K logic cells. The EV is designed for multimedia, automotive ADAS, surveillance, and other embedded vision applications.

Zynq UltraScale+ MPSoC comparison chart
(click image to enlarge)

The six sub-models of the new dual-core Zynq UltraScale+ MPSoC CG — ZU2CG, ZU3CG, ZU4CG, ZU5CG, ZU6CG, ZU7CG, and ZU9CG — differ only in their FPGA capabilities. Common features include 32KB I/D L1 cache per core, 1MB L2, and 256KB on chip memory attached to the Cortex-A53 subsystem, and 32KB I/D L1 cache per core for the Cortex-R5 chips with 128KB memory per core.

The CG supports a range of RAM types up to LPDDR4 with ECC, as well as NAND and 2x quad-SPI memories. The SoC supports PCIe Gen2 x4, dual USB 3.0 ports, SATA 3.1, DisplayPort, and up to four Tri-mode GbE ports. Other supported peripherals include CAN 2.0B, SDIO, UARTs, I2C, SPI, and GPIO.

Additional CG features include power management and a security chip with RSA, AES, and SHA support. Developers can start working with the CG by using the Vivado Design Suite version 2016.3 in 4Q 2016 prior to the 1H 2017 production launch. Presumably, the CG will also share the newly announced Android 5.1 and Mentor Embedded Linux support of the “pin migration compatible” EG and EV models.

New Zynqs gain Android 5.1 and Mentor Embedded Linux

The Xilinx Zynq UltraScale+ MPSoC family was originally announced with a Xilinx PetaLinux distribution, SDK, and BSP. Now Mentor Graphics has announced support for the MPSoC family with its Mentor Embedded Linux distribution plus its Nucleus RTOS and a new Android 5.1 “Lollipop” build. The company also announced Zynq UltraScale+ MPSoC support within its automotive focused Mentor Embedded Hypervisor and OpenAMP compatible Mentor Embedded Multicore Framework products.

The Zynq UltraScale+ MPSoC isolates hardware resources to allow a high-level OS such as Linux or Android to co-exist with safety critical functions run by a RTOS on the Cortex-R5 MCUs, says Mentor Graphics. The company is taking advantage of this hardware virtualization support with solutions such as Mentor Embedded Hypervisor and Mentor Embedded Multicore Framework.

“Architects are now beginning to design Zynq UltraScale+ MPSoC into complex systems comprised of one or more Linux or RTOSes running on a hypervisor for the ARM Cortex -A53 cores, and RTOS or bare-metal environments executing on the ARM Cortex-R5 cores,” says Mentor Graphics. Developers can implement features such as voice recognition, rich user interfaces, and extensive customization “without compromising safety and security,” says the company.

The Android 5.1 support draws from Mentor’s port of Android Open Source Project (AOSP) to the MPSoC platform. The original Zynqs also supported Android, but Linux has always been the main focus. The new port provides “many opportunities for the deployment of Android into non-traditional markets,” says the company.

Further information

The dual-core CG version of the Zynq UltraScale+ MPSoC will reach production in 1H 2017. More information on the MPSoC CG and how it compares with the EG and EV models may be found in this Xilinx Zynq UltraScale+ MPSoC product page. The Mentor Graphics ports for MPSoC will roll out throughout 2016, with the Android 5.1 support due in the third quarter. More information may be found at this Mentor Embedded for Xilinx page.

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